Pulse testing estimates SOC-dependent internal resistance by applying brief current steps and measuring the resulting voltage change. For a pulse with current magnitude (I), the effective resistance is calculated as (R_O=\Delta U/|I|), where (\Delta U=|U_1-U_0|) is the voltage difference before and during the pulse. Repeating this test at different States of Charge (SOC) typically shows relatively stable resistance through the middle SOC range, with a noticeable increase near both low and high SOC.
The key result is a U-shaped SOC relationship: lithium-ion cells generally exhibit their lowest and most stable effective pulse resistance around roughly 30%–70% SOC, while resistance rises as the cell approaches either empty or fully charged conditions.
How Pulse Testing Evaluates Resistance
Applying controlled current pulses
A battery tester first establishes the cell at a defined SOC and rest condition. It then applies a short charging or discharging current pulse while recording the cell voltage at high time resolution.
The test can be repeated across many SOC points to create a resistance map rather than relying on a single resistance value.
Measuring the transient voltage response
The tester compares the voltage immediately before the pulse, (U_0), with the voltage during the pulse, (U_1). The observed voltage change is:
[ \Delta U = |U_1-U_0| ]
The effective pulse resistance is then estimated as:
[ R_O=\frac{\Delta U}{|I|} ]
This is a DC pulse or effective resistance, not necessarily the same value that would be obtained from electrochemical impedance spectroscopy (EIS).
Capturing short-timescale behavior
The voltage response may include an immediate step followed by slower relaxation or polarization. Consequently, the measured resistance depends on factors such as pulse duration, sampling time, current direction, temperature, and the cell’s prior operating history.
A millisecond-scale measurement emphasizes different processes than a pulse lasting several seconds. Test conditions must therefore be kept consistent when comparing cells or SOC points.
What the SOC Relationship Typically Looks Like
Stable resistance in the middle SOC range
Across approximately 30%–70% SOC, effective internal resistance is often relatively flat. This region generally provides the most consistent voltage response under comparable pulse conditions.
The exact values and boundaries vary with cell chemistry, design, temperature, aging, and test protocol.
Higher resistance near low SOC
As SOC becomes low, the cell commonly shows a larger voltage drop for the same current pulse. The calculated resistance therefore increases.
This behavior limits the power that can be delivered safely near depletion and can cause a battery-management system to reduce available current.
Higher resistance near high SOC
Resistance also tends to rise near the upper SOC limit. A fully charged cell may therefore exhibit less favorable pulse-power behavior than a cell in the middle SOC range, despite having more stored energy.
This is one reason that maximum allowable charge and discharge currents are often made dependent on both SOC and temperature.
What the Measured Resistance Represents
Ohmic contribution
The immediate voltage step partly reflects ohmic resistance from the electrolyte, electrodes, separator, current collectors, tabs, contacts, and other conductive interfaces.
This component responds quickly to a current change and is strongly influenced by cell construction and electrical connections.
Polarization contribution
The measured pulse response also includes polarization resistance associated with charge-transfer reactions and ion transport. Diffusion limitations can cause the voltage to continue changing during a pulse rather than settling instantly.
For this reason, pulse-derived resistance is best understood as an application-relevant effective resistance under a defined pulse profile.
Temperature and aging effects
Resistance is not determined by SOC alone. Lower temperature, aging, high storage temperature, prolonged high SOC, and deep cycling can increase resistance and alter the shape of the SOC curve.
A meaningful SOC comparison should therefore control or record temperature, current amplitude, pulse duration, rest time, and cell age.
Why the Measurement Matters
Estimating available power
Internal resistance converts part of the battery’s electrical energy into heat and causes terminal voltage to fall under load. As the voltage drop grows, the usable output power declines.
For a simplified load model, maximum power transfer occurs when external load resistance equals battery internal resistance. Real battery systems also impose voltage, thermal, and safety limits, so this condition is a reference rather than a complete operating rule.
Refining battery-management limits
SOC-dependent resistance data helps a BMS set more realistic current limits. The system can reduce power requests when the cell is near either SOC extreme, cold, aged, or otherwise operating under conditions that increase voltage sag.
This improves protection against undervoltage, overvoltage, excessive heating, and inaccurate power estimates.
Comparing cell designs and packs
Automated, multi-channel testers can apply identical pulse sequences to many cells. The resulting resistance and voltage-response data supports cell screening, power-capability evaluation, and validation of equivalent-circuit models.
For identical cells connected in parallel, the idealized equivalent resistance decreases approximately as (R_{\text{block}}=R_{\text{cell}}/N). Actual modules can deviate because of unequal cell properties, interconnect resistance, temperature gradients, and current-sharing differences.
Understanding the Trade-offs
Pulse testing is not the same as EIS
A pulse test produces a practical resistance estimate under a specified transient load. EIS separates frequency-dependent electrochemical contributions and can provide more detailed diagnostic information.
Neither method universally replaces the other: pulse testing is often more directly relevant to real power demands, while EIS can help identify the physical processes behind the measured response.
A single resistance value can mislead
Reporting one resistance number without its SOC, temperature, pulse duration, current, and rest conditions removes essential context. Two valid tests can produce different values simply because they measure different timescales.
Resistance should therefore be reported together with the complete test protocol.
Voltage drop is not purely resistive
The observed (\Delta U) can include open-circuit-voltage changes, charge-transfer polarization, diffusion effects, and measurement-system artifacts. Treating the entire response as a fixed resistor is a useful approximation, but not a complete electrochemical description.
High SOC and low SOC are operationally different
Both SOC extremes may show increased resistance, but their safety implications differ. Low SOC is commonly associated with greater discharge voltage sag, while high SOC can increase charge-related constraints and aging sensitivity.
Current limits should be designed around the measured behavior rather than assuming that resistance changes symmetrically in every operating condition.
How to Apply This to Your Project
A useful test plan should map resistance across SOC while controlling temperature, current, pulse duration, rest time, and cell history.
- If your primary focus is BMS calibration: Measure pulse resistance across the full SOC range and use the results to define SOC- and temperature-dependent current and power limits.
- If your primary focus is cell power capability: Use application-relevant discharge pulses and record voltage sag, heating, and recovery rather than relying only on a nominal resistance value.
- If your primary focus is cell quality or aging: Repeat the same pulse protocol over cycling and storage conditions to track irreversible resistance growth.
- If your primary focus is electrochemical diagnosis: Combine pulse testing with EIS or other diagnostic methods to distinguish fast ohmic effects from slower polarization and diffusion behavior.
A controlled SOC-dependent pulse map provides the practical evidence needed to predict voltage sag, available power, thermal stress, and battery-management limits.
Summary Table:
| SOC Range | Typical Resistance Behavior | Practical Implication |
|---|---|---|
| 30%–70% | Stable, relatively flat | Consistent power delivery |
| Low SOC | Higher (increases) | Reduced discharge power, risk of undervoltage |
| High SOC | Higher (increases) | Reduced charge acceptance, aging stress |
Optimize your battery R&D with precise SOC-dependent resistance testing. KINTEK provides comprehensive laboratory equipment for battery R&D and advanced materials research. Our portfolio covers the entire cell fabrication workflow—from slurry mixing, coating, and precision pressing to cell assembly, testing systems, and beyond. Enhance your power capability evaluation and BMS calibration. Contact us today to learn more about our solutions tailored to your needs.