Use a precision shunt with an isolated measurement chain. In high-voltage battery evaluation equipment, the shunt is installed in series with the main DC path, and the measurement system determines current from its small differential voltage drop. Because the shunt may be at a high common-mode potential relative to the control electronics, the design generally requires galvanic isolation between the sensing circuitry, ADC, power supplies, and control CPU. High-resolution sampling and time integration then support ampere-hour counting, capacity tracking, SOC estimation, and instantaneous power calculation.
The required architecture is a precision differential shunt measurement front end followed by high-resolution signal conversion and galvanic isolation. The isolation boundary must account for both signal paths and power paths; otherwise, a high-quality ADC alone cannot protect the low-voltage control system.
Why the Shunt Requires an Isolation Architecture
The Measurement Is Differential but the System Is Not
A shunt produces a small voltage, typically proportional to current:
[ V_{\text{shunt}} = I \times R_{\text{shunt}} ]
The voltage of interest is the difference between the shunt terminals. However, both terminals can be at a substantial common-mode voltage relative to the CPU, communications interface, or low-voltage ground.
A differential measurement therefore does not automatically provide galvanic isolation. The front end must tolerate the battery-side common-mode voltage while preserving the small differential signal.
Shunt Location Determines the Isolation Requirement
A low-side shunt may place one terminal near the battery negative reference, which can simplify the analog interface. It can also disturb the system's ground reference and is not suitable for every battery topology.
A high-side shunt preserves the load's connection to the system return but places the sensing circuit at a higher common-mode voltage. It generally demands a high-common-mode differential amplifier, isolated amplifier, isolated ADC, or an equivalent isolated measurement architecture.
The phrase “the shunt operates at full battery system potential” is therefore topology-dependent. The critical design fact is that the sensing electronics may be exposed to hazardous or elevated common-mode voltage even though the measured shunt signal is only a few millivolts.
The Required Signal Processing Chain
Precision Shunt and Kelvin Connections
The shunt should be a stable, low-inductance precision alloy resistor selected for its resistance tolerance, temperature coefficient, power rating, and pulse capability.
Kelvin, or four-wire, connections should be used where practical. Separate force and sense connections prevent current-carrying PCB traces and connection resistance from becoming part of the measured voltage.
The shunt must also be sized carefully. A lower resistance reduces power loss and heating but produces a smaller signal, increasing the demands on the amplifier, ADC, layout, and noise filtering.
Differential Amplification and Protection
The shunt voltage normally requires a dedicated differential front end before conversion. This stage should provide:
- High common-mode rejection
- A defined gain matched to the expected current range
- Input protection for switching transients and wiring faults
- Filtering for inverter, charger, and contactor noise
- Low offset and drift for accurate charge integration
The amplifier must remain within its input common-mode and output swing limits throughout the battery's voltage and current operating range. Protection components and filters must be selected so they do not introduce excessive imbalance between the two sense inputs.
High-Resolution Conversion
A high-resolution ADC, such as a 24-bit delta-sigma converter, can be appropriate when the system must resolve small currents over a wide dynamic range. Delta-sigma converters also provide useful noise-shaping and digital filtering characteristics.
However, nominal resolution is not the same as usable resolution. SOC accuracy depends on effective number of bits, offset stability, gain accuracy, sampling timing, reference stability, and the quality of the analog layout.
Sampling rates such as 4,000 samples per second may be suitable for capturing dynamic battery-test behavior and computing instantaneous power. The required rate should be established from the fastest current transients, control-loop requirements, and anti-aliasing design rather than treated as a universal specification.
Synchronized Voltage and Current Sampling
Current and battery-voltage measurements should use a common timing reference or a known time relationship. Instantaneous power is calculated as:
[ P(t) = V_{\text{battery}}(t) \times I(t) ]
If the two channels are sampled at materially different times during fast transients, the calculated power can contain errors even when each channel is individually accurate.
Synchronized measurements also improve energy tracking and help correlate current events with charger, load, and protection behavior.
Where the Galvanic Isolation Boundary Belongs
Isolated ADC or Isolated Digital Data Link
One robust architecture places the analog front end and ADC on the battery-side of the isolation barrier. The converted data then crosses the barrier through an isolated digital interface or a suitable isolated communication link.
This approach keeps sensitive analog signals physically close to the shunt and avoids sending millivolt-level signals across a long isolation boundary. The isolation device must meet the required working voltage, transient rating, creepage, clearance, timing, and electromagnetic compatibility requirements.
Isolated Amplifier Before a Ground-Referenced ADC
Another architecture uses an isolation amplifier or isolated analog signal device after the differential shunt amplifier. The control-side ADC then measures the isolated output.
This can integrate with an existing control platform, but the isolation amplifier's offset, linearity, bandwidth, temperature drift, and output noise become part of the current-measurement error budget.
Isolated Power for the Sensing Electronics
The isolation barrier must include power as well as signal paths. The battery-side amplifier, ADC, reference, and related circuitry require an isolated power supply if they cannot share the control unit's ground.
Parasitic capacitance across the isolated DC/DC converter and signal isolators can still transfer common-mode transient currents. The power architecture therefore needs appropriate filtering, shielding, grounding, and transient-current management.
Optical Couplers and Modern Alternatives
High-speed optical couplers can provide the required digital isolation, particularly where established isolation interfaces already exist. Their propagation delay, channel matching, temperature behavior, and data-rate limits must be considered.
Other isolated digital technologies may offer better timing consistency or lower power, but the selection should be based on the required isolation rating, transient immunity, bandwidth, and system certification requirements rather than on the isolation method alone.
How the Architecture Supports SOC Estimation
Ampere-Hour Counting
The basic charge estimate is obtained by integrating measured current over time:
[ Q = \int I(t),dt ]
In discrete form:
[ Q_k = Q_{k-1} + I_k \Delta t ]
This is often called coulomb counting or ampere-hour counting. The current samples must have a reliable time base, consistent sign convention, and sufficiently low offset to prevent accumulated error.
Capacity Tracking
The integrated current is used to track charge entering and leaving the battery during evaluation cycles. Comparing the accumulated charge with voltage, temperature, cycle state, and test limits supports capacity characterization.
The shunt measurement does not independently determine true SOC. It provides one important input to the SOC estimator, while the estimator's accuracy also depends on initial SOC, battery history, charge efficiency, temperature, self-discharge, and the selected battery model.
Offset and Drift Compensation
A small current-measurement offset becomes a significant SOC error after long integration periods. The design should therefore include zero-current calibration, offset monitoring, temperature characterization, and periodic correction where the test procedure allows it.
Gain error affects the scale of the accumulated charge, while offset error creates an error that grows with elapsed time. These two error types should be analyzed separately.
Understanding the Trade-offs
Resolution Versus Power Loss
A larger shunt resistance produces a larger measurable voltage and can improve signal-to-noise performance. It also increases (I^2R) loss, self-heating, voltage drop, and disturbance to the battery test.
A smaller shunt reduces insertion loss but demands a quieter, lower-offset signal chain. The correct value is a system-level compromise between accuracy, thermal behavior, efficiency, and allowable test-path voltage drop.
Bandwidth Versus Noise
High sampling rates and wide analog bandwidth improve transient visibility. They also admit more switching noise and can make the measurement more sensitive to layout, shielding, and anti-aliasing weaknesses.
For SOC integration, a stable and well-characterized measurement is usually more important than maximum bandwidth. For protection or dynamic characterization, higher bandwidth may be necessary, potentially requiring separate measurement paths.
Isolation Versus Complexity
Galvanic isolation protects the low-voltage control system and allows the sensing electronics to float at the battery-side potential. It adds isolated power supplies, isolation components, layout constraints, latency, component tolerances, and additional verification requirements.
Isolation should be designed as a complete signal-and-power subsystem. Isolating only the data line while leaving an unintended ground, shield, power, or communication return path can defeat the intended safety boundary.
Resolution Versus Conversion Latency
Delta-sigma ADCs can provide excellent low-frequency resolution, but their digital filters introduce latency and settling behavior. This is acceptable for many SOC and capacity calculations but may be unsuitable for the fastest protection loop unless a separate faster path is provided.
The control architecture should distinguish between accurate energy/SOC measurement and fast fault response when their timing requirements differ.
Common Pitfalls to Avoid
Treating Nominal ADC Bits as SOC Accuracy
A 24-bit ADC does not guarantee 24 bits of useful current information. Shunt tolerance, amplifier offset, thermal drift, reference error, common-mode effects, PCB leakage, and digital filtering all contribute to the final result.
The complete error budget should be evaluated at the minimum, nominal, and maximum current ranges.
Ignoring Thermal Effects
Shunt resistance changes with temperature, and the shunt can heat itself significantly during high-current testing. That changes the measured voltage for a given current and can create systematic SOC and capacity errors.
Thermal design, resistor characterization, and temperature compensation should be considered part of the measurement architecture.
Integrating Uncalibrated Offset
Even a small residual offset can accumulate into a large charge error. Zero-current calibration and long-duration drift testing are essential before relying on coulomb counting for capacity or SOC conclusions.
Sampling Without Anti-Aliasing or Timing Control
Switching converters, PWM inverters, contactors, and test-fixture wiring can introduce high-frequency components that alias into the sampled current signal. Analog filtering, appropriate ADC configuration, and controlled sampling timing are required.
Voltage and current channels should also be time-aligned when calculating power and energy.
Making the Right Choice for Your Goal
The appropriate architecture depends on whether the priority is safe measurement, precise SOC integration, fast transient capture, or low insertion loss.
- If your primary focus is galvanic safety: Place the sensing electronics on the battery side where necessary, use isolated power, and transfer the measurement data across a verified isolation barrier.
- If your primary focus is SOC and capacity accuracy: Use a precision Kelvin-connected shunt, low-offset differential signal chain, high-resolution ADC, stable timing, and calibrated current integration.
- If your primary focus is instantaneous power and dynamic testing: Synchronize voltage and current sampling, select sufficient bandwidth, and design anti-aliasing around the fastest relevant transients.
- If your primary focus is minimizing test-path losses: Use a lower-resistance shunt and compensate with a lower-noise, lower-drift front end while verifying thermal and calibration performance.
- If your primary focus is fast protection: Do not rely solely on a high-resolution delta-sigma path; provide a measurement or comparator path whose latency matches the protection requirement.
A well-designed shunt system treats isolation, analog accuracy, sampling behavior, thermal stability, and SOC algorithms as one measurement architecture rather than as independent components.
Summary Table:
| Architecture Component | Key Requirement | Typical Approach |
|---|---|---|
| Shunt Configuration | Low-inductance, precision alloy, Kelvin connections | Four-wire connection to reduce error |
| Differential Front End | High CMRR, low offset, input protection | Instrumentation amplifier with filtering |
| ADC | High resolution and dynamic range | 24-bit delta-sigma ADC |
| Isolation Barrier | Galvanic isolation for signal and power | Isolated ADC or digital isolator with isolated DC/DC |
| Sampling synchronization | Voltage and current aligned in time | Shared timing reference |
| Calibration | Offset and gain correction | Periodic zero-current calibration |
Ensure accurate and safe battery testing with KINTEK's advanced laboratory equipment. Our precision shunt measurement and isolation solutions are designed for optimal SOC estimation. Contact our experts today to enhance your battery evaluation systems. Contact us now.